Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture

نویسندگان

  • John Oliver
  • Diana Franklin
  • Frederic T. Chong
  • Venkatesh Akella
چکیده

This paper investigates the impact of proper tile size selection on the power the power consumption for tile-based processors. We refer to this investigation as a tile granularity study. This is accomplished by distilling the architectural cost of tiles with different computational widths into a system metric we call the Granularity Indicator (GI). The GI is then compared against the bisection bandwith of algorithms when partitioned across multiple tiles. From this comparison, the tile granularity that best fits a given set of algorithms can be determined, reducing the system power for that set of algorithms. When the GI analysis is applied to the Synchroscalar tile architecture [1], we find that Synchroscalar’s already low power consumption can be further reduced by 14% when customized for execution of the 802.11a reciever. In addition, the GI can also be a used to evaluate tile size when considering multiple applications simultaneously, providing a convenient platform for hardware-software co-design.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

On-chip Interconnection Architecture of the Tile Processor Imesh, the Tile Processor Architecture's On-chip Interconnection Network, Connects the Multicore Processor's Tiles with Five 2d Mesh Networks, Each Specialized for a Different Use. Taking Advantage of the Five Networks, the C

......As the number of processor cores integrated onto a single die increases, the design space for interconnecting these cores becomes more fertile. One manner of interconnecting the cores is simply to mimic multichip, multiprocessor computers of the past. Following past practice, simple busbased shared-memory multiprocessors can be integrated onto a single piece of silicon. But, in taking thi...

متن کامل

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design in­ tuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based embedded architecture targeted for multi-rate signal processing applica­ tions. We present a preliminary design of the ...

متن کامل

Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications

We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be attained through parallelization. The importance of adequate inter-core interconnect is also demonstrated. We discuss the impact of having multiple frequency and voltage domains on chip to reduce the power consumption w...

متن کامل

Selecting the Optimal Tile Size for Low-Power Tile-Based Rendering

Power-aware graphics architectures are receiving more attention recently. In this paper we analyze rendering techniques suitable for low power devices. One technique that looks promising is Tile Rendering. This technique decomposes a scene into tiles and renders each tile independently. For several scenes we compute a tile size that allows most triangles to be rendered without being divided int...

متن کامل

Memory Bandwidth Requirements of Tile-Based Rendering

Because mobile phones are omnipresent and equipped with displays, they are attractive platforms for rendering 3D images. However, because they are powered by batteries, a graphics accelerator for mobile phones should dissipate as little energy as possible. Since external memory accesses consume a significant amount of power, techniques that reduce the amount of external data traffic also reduce...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • Trans. HiPEAC

دوره 1  شماره 

صفحات  -

تاریخ انتشار 2007